1. Field of the Invention
This invention relates to a technique of driving a liquid crystal display, and more particularly to a method of driving a liquid crystal display that is adaptive for improving a picture quality.
2. Discussion of the Related Art
Generally, an active matrix liquid crystal display (LCD) controls a light transmissivity of a liquid crystal using an electric field applied to the liquid crystal. To this end, as shown in FIG. 1, the active matrix LCD includes a liquid crystal display panel 2 having liquid crystal cells arranged between two sheets of transparent substrates in a matrix form, a gate driver 6 connected to gate lines GL1 to GLm of the liquid crystal display panel 2, and a data driver 4 connected to data lines DL1 to DLn of the liquid crystal display panel 2.
The gate driver 6 sequentially applies a scanning pulse to m gate lines GL1 to GLm to drive thin film transistors (TFTs) connected to the corresponding gate line. The data driver 4 supplies a data corresponding to a brightness value of a video data to n data lines DL1 to DLn in synchronization with the scanning pulses that are sequentially applied to the gate lines GL1 to GLm.
More specifically, the conventional LCD sequentially turns on and off the gate lines GL1 to GLm during one frame and supplies a data corresponding to the turned-on gate lines GL1 to GLm to the data lines DL1 to DLn, thereby displaying a picture.
FIG. 2 shows driving waveforms of the conventional gate driver and the conventional data driver. Referring to FIG. 2, the gate driver 6 receives a clock signal (e.g., 22 μs in the case of XGA) and a gate output enable (GOE) signal from an external control circuit (not shown). The gate driver 6 supplied with the clock signal and the GOE signal sequentially applies a scanning pulse SP to the 1st to mth gate lines GL1 to GLm in synchronization with the clock signal. The data driver 4 applies picture data D to the data lines DL1 to DLn in synchronization with the scanning pulse SP that is sequentially applied to the gate lines GL1 to GLm.
The GOE signal is divided into first to third GOE signals GOE1 to GOE3. FIG. 3 schematically shows a relationship between the GOE signals and the gate lines. As shown in FIG. 3, the first gate output enable signal GOE1 is applied to the (3i+1)th gate lines GL1, GL4, etc. (where i is a non-negative integer). The second gate output enable signal GOE2 is applied to the (3i+2)th gate lines GL2, GL5, etc. The third gate output enable signal GOE3 is applied to the (3i+3)th gate lines GL3, GL6, etc.
The gate lines GL1 to GLm remain at, or are forced to return to, a low state when the first to third gate output enable signals GOE1 to GOE3 assume a high state. For example, whenever the first gate output enable signal GOE1 assumes a high state, the (3i+1)th gate lines (GL1, GL4, . . . ) are at a low state.
Such gate output enable signals GOE1 to GOE3 are utilized to prevent a so-called crosstalk phenomenon between the adjacent pixel cells. The first gate output enable signal GOE1 is set at a high state between a scanning pulse SP applied to the (3i+1)th gate lines (GL1, GL4, . . . ) and a scanning pulse SP applied to the (3i+2)th gate lines (GL2, GL5, . . . ) to define the trailing edge of the gate pulse applied to (3i+1)th gate lines. In other words, the first gate output enable signal GOE1 is raised to a high state before a clock signal for applying the scanning pulse SP to the (3i+2)th gate lines (GL2, GL5, . . . ) is raised to a high state.
Accordingly, a point in time at which the scanning pulse SP applied to the (3i+1)th gate lines (GL1, GL4, . . . ) is changed into a low state is always set prior to a point in time at which the scanning pulse SP applied to the next (3i+2)th gate lines (GL2, GL5, . . . ) is raised to a high state, and is determined by the leading edge of the gate output enable signal GOE1. In other words, the scanning pulses SP, each of which originally spans from the leading edge of one clock pulse of the clock signal to the leading edge of the next clock pulse, are shaped to have a specific margin between two adjacent pulses. This way, it becomes possible to prevent the crosstalk phenomenon.
Similarly, the second gate output enable signal GOE2 is set at a high state between a scanning pulse SP applied to the (3i+2)th gate lines (GL2, GL5, . . . ) and a scanning pulse SP applied to the next (3i+3)th gate lines (GL3, GL6, . . . ). The third gate output enable signal GOE3 is set at a high state between a scanning pulse SP applied to the (3i+3)th gate lines (GL3, GL6, . . . ) and a scanning pulse SP applied to the next (3i+1)th gate lines (GL4, GL7, . . . ).
However, the conventional driving scheme described above suffers from the following drawbacks. As shown in FIG. 4, when a scanning pulse SP is applied to, for example, 295 the (m−10)th gate line GLm-10 by the gate driver 6, the liquid crystal display panel 2 is divided into a current frame 16 and a previous frame 18 separated by the (m−10)th gate line GLm-10. A picture to be displayed in the current frame is displayed in the current frame 16 while a picture that has been displayed in the previous frame is displayed in the previous frame 18.
Accordingly, if a moving picture shifts from the right side of the liquid crystal display panel 2 to the left side thereof, a moving picture 20 displayed in the current frame 16 and a moving picture 22 displayed in the previous frame 18 go amiss at the (m−10)th gate line GLm-10, as shown in FIG. 5A. This means that, to the observer, the previous data picture is seen to be interposed on the current data picture at portions 24 at which the moving picture 20 displayed in the current frame 16 has been shifted, as shown in FIG. 5B. When the previous data picture overlaps with the current data picture in this manner, a motion blur phenomenon is generated, and the picture quality of the liquid crystal display panel 2 accordingly deteriorates.
Each pixel of the liquid crystal display panel 2 can be represented by an equivalent circuit in FIG. 6. In FIG. 6, the pixel includes a thin film transistor (TFT) connected to a gate line GL, a data line DL, and a pixel electrode PE. The pixel also includes a liquid crystal cell Clc connected to a drain terminal of the TFT through the pixel electrode PE and a common voltage line CL carrying a common voltage Vcom. The pixel of the liquid crystal display panel 2 further includes a parasitic capacitor Cgs formed between the drain terminal of the TFT and the gate line GL, and a storage capacitor Cst formed between the drain terminal (and/or pixel electrode) of the TFT and a ground voltage source GND.
FIG. 7 shows a timing chart for the gate pulse SP and the voltage Vlc across the liquid crystal cell Cls. When a gate high voltage Vgh is applied to the gate line GL of the liquid crystal display panel 2, a data signal D is applied to the data line DL. As shown in FIG. 7, when the gate line GL is raised to the high voltage Vgh, the TFT is turned on, and the data pulse D applied to the data line DL is transferred to the drain side of the TFT (hence, to the pixel electrode PE). However, when the gate line GL returns to its low state (Vgl) at time t1, the voltage VD applied across the liquid crystal cell Clc undesirably drops by an amount ΔVp. This causes a brightness deterioration in the liquid crystal display panel 2, i.e., a picture quality deterioration. A voltage drop amount ΔVp in the voltage applied across the liquid crystal cell Cls is determined by the following equation:ΔVp=(Cgs/(Cgs+Cst+Clc))*(Vgh−Vgl),  (1)where Clc represents a capacitance of the liquid crystal cell, Vgh represents a gate high voltage value; and Vgl represents a gate low voltage value.
In the equation (1), the parasitic capacitor Cgs, the storage capacitor Cst, the gate high voltage value Vgh, and the gate low voltage value Vgl are fixed, whereas a capacitance value of the liquid crystal cell Clc is influenced by a displayed picture (i.e., the voltage applied across the liquid crystal cell in the previous frame). This is because the capacitance value Clc is proportional to the dielectric constant ε of the liquid crystal material, and the dielectric constant ε of the liquid crystal material varies depending upon the electric field applied thereto. If a stationary picture were always displayed on the liquid crystal display panel 2, then a voltage drop amount ΔVp of the data pulse would be predicted because a capacitance value of the liquid crystal cell Clc is constant. In such a case, the voltage drop amount ΔVp of the data pulse can be compensated, and accordingly, a picture quality deterioration in the liquid crystal display panel 2 can be prevented.
If a moving picture is displayed on the liquid crystal display panel 2, however, a voltage drop amount ΔVp of the data pulse cannot be predicted because the capacitance value of the liquid crystal cell Clc varies. Thus, the voltage drop amount ΔVp of the data signal applied to the liquid crystal cell Clc cannot be sufficiently compensated, and a picture quality deterioration results.